Publications and Given Talks


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Patents:

[1] Inventors: Andre Costi Nacul, Francesco Regazzoni, and Marcello Lajolo, Assignee: NEC Laboratories America, Inc. (Princeton, NJ), Hardware scheduled SMP architectures, Application Number: 11/947278, United States patent number: 7,502,378, Filed: 11 November, 2007, Issue date: 5 June, 2008.


Journal Papers and Book Chapters:

[2] Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, and François-Xavier Standaert, Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags, in Journal of Cryptographic Engineering, Volume 1, Issue 1 (2011), Springer

[1] Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, and Paolo Ienne, Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology, in Transactions on Computational Science 4, 2009


Conference Papers:

[26] Leandro Fiorin, Alberto Ferrante, Kostantinos Padarnitas, and Francesco Regazzoni Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation, to appear in Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC) 2012, Sydney, Australia, 30 January - 2 February 2012

[25] Stéphanie Kerckhof, François Durvaux, Nicolas Veyrat-Charvillon, Francesco Regazzoni, Guerric Meurice de Dormale, and François-Xavier Standaert, Low Cost FPGA Implementations of the SHA-3 Finalists, in Proceedings of 10th Smart Card Research and Advanced Application Conference (CARDIS) 2011, Leuven, Belgium, 14-16 September 2011

[24] Marcel Medwed, Christophe Petit, Francesco Regazzoni, Mathieu Renauld, and François-Xavier Standaert, Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks, in Proceedings of 10th Smart Card Research and Advanced Application Conference (CARDIS) 2011, Leuven, Belgium, 14-16 September 2011

[23] Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, and Israel Koren, Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation, in Proceedings of 7th Workshop on RFID Security and Privacy (RFIDSec) 2011, Amherst, Massachussets, 26–28 June 2011

[22] Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, and Paolo Ienne, A First Step Towards Automatic Application of Power Analysis Countermeasures, in Proceedings of 48th Design Automation Conference (DAC) 2011, San Diego, Califorina, 5-9 June 2011

[21] Alessandro Cevrero, Francesco Regazzoni, Michael Schwander, Stéphane Badel, Paolo Ienne, and Yususf Leblebici Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library, in Proceedings of 48th Design Automation Conference (DAC) 2011, San Diego, Califorina, 5-9 June 2011

[20] Francesco Regazzoni, Wang Yi, and François-Xavier Standaert FPGA Implementations of the AES Masked Against Power Analysis Attacks, in Proceedings of 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE) 2011, Darmstadt, Germany, 24-25 February 2011

[19] Jean-Francois Gallais, Johann Großschädl, Neil Hanley, Markus Kasper, Marcel Medwed, Francesco Regazzoni, Joern-Marc Schmidt, Stefan Tillich, and Marcin Wojcik Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software, in Proceedings of 2nd International Conference on Trusted Systems, (INTRUST) 2010, Beijing, China, 13-15 December 2010

[18] Alessandro Barenghi, Luca Breveglieri, Israel Koren, Gerardo Pelosi, and Francesco Regazzoni Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs, in Proceedings of 5th Workshop on Embedded Systems Security (WESS) 2010, Scottsdale, Arizona, USA, 24 October 2010

[17] Marcel Medwed, François-Xavier Standaert, Johann Großschädl, and Francesco Regazzoni, Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices, in Proceedings of Progress in Cryptology - Africacrypt 2010, Stellenbosch, South Africa, 3-6 May 2010

[16] Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto, A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation, in Proceedings of Design, Automation and Test in Europe (DATE) 2010, Dresden, Germany, 6-12 March 2010

[15] Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier van Damme, Giacomo de Meulenaer, Junfeng Fan, Frank Gurkaynak, Tim Güneysu, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, and Leif Uhsadel, The Certicom Challenges ECC2-X, in Proceedings of Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS'09), Lausanne (Switzerland), 9-10 September 2009

[14] Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, and Paolo Ienne, A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions, in Proceedings of 11th Cryptographic Hardware and Embedded Systems International Workshop (CHES 09), Lausanne, Switzerland, 6-9 September 2009

[13] Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, and Israel Koren, Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?, in Proceedings of 23nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08), Boston, MA, USA, Porto, Portugal, 1-3 October 2008

[12] Guido Marco Bertoni, Luca Breveglieri, Roberto Farina, and Francesco Regazzoni, A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm, in Proceedings of Secrypt 2008, Porto, Portugal, 26-29 July 2008

[11] Joao Otero, Francesco Regazzoni, and Marcello Lajolo, Rapid Creation of Application Models from Bandwidth Aware Core Graphs, in Proceedings of IP Based SoC Design 2007, Grenoble, France, 5-6 December 2007

[10] Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, and Christof Paar, Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits, in Proceedings of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, 26-28 September 2007

[9] Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici and Paolo Ienne, Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, 16-19 July 2007

[8] Francesco Regazzoni, Ivano Bonesana, Maksim Djakov, and Amanda Mattiuz, Tairona, an Open Source Platform for On-Line Meeting and Tutoring, in Proceedings of World Conference on Educational Multimedia, Hypermedia and Telecommunications (ED-MEDIA 07), Vancouver, Canada, 25-29 June 2007

[7] Andre Costi Nacul, Francesco Regazzoni, and Marcello Lajolo, Hardware Scheduling Support in SMP Architectures, in Proceedings of Design, Automation and Test in Europe (DATE) 2007, Nice, France, 16-20 April 2007

[6] Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, and Kai Schramm Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes, in Proceedings of IEEE International Conference on VLSI Design & Embedded Systems, Bangalore, India, 6-10 January 2007 (authors in alphabetical order).

[5] Guido Marco Bertoni, Luca Breveglieri, Roberto Farina and Francesco Regazzoni, Speeding Up AES By Extending a 32 bit Processor Instruction Set, in Proceedings of Application Specific Architecture and Processors (ASAP) 2006, Steamboat Springs, Colorado, USA, 11-13 September, 2006 (authors in alphabetical order).

[4] Satish Chandra, Francesco Regazzoni, Marcello Lajolo, Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach, in Proceedings of Great Lake Symposium on Very Large System Integration (GLSVLSI) 2006, Philadelphia, Pennsylvania, USA 30 April - 2 May, 2006.

[3] Francesco Regazzoni and Marcello Lajolo, Hardware/Software Partitioning and Interface Synthesis in Networks On Chip, in Proceedings of IP Based SoC Design  2005, Grenoble, France, 7-8 December, 2005.

[2] Francesco Regazzoni, Andre Costi Nacul, and Marcello Lajolo, Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures, in Proceedings of Forum on Specification and Design Languages (FDL), Lausanne, Switzerland, 27-30 September, 2005.

[1] Francesco Regazzoni and Marcello Lajolo, Interface Synthesis in Multiprocessing Systems-On-Chips, in Proceedings of IP Based SoC Design 2004, Grenoble, France, 8-9 December, 2004.


Given Talks:

[5] A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions, University Booth demonstration at 46 Design Automation Conference (DAC), San Francisco, California, USA, July 26-31, 2009.

[4] DPA resistant design flow for design of secure coprocessors, PhD Forum of Design Automation and Testing in Europe (DATE) 2008, Munich, Germany, 10-14 March, 2008.

[3] Design Flow for enabling DPA analysis and DPA resistant design, University Booth of 44rd Design Automation Conference (DAC) 2007, San Diego, California, USA, 4-8 June, 2007.

[2] Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach, invited talk at IEEE EDP 2006 Workshop, Monterey California, USA, 13-14 April, 2006.

[1] Early power and performance optimization of algorithm implementation on ARM processors, Exhibition theater of Design Automation and Testing in Europe (DATE) 2006, Munich, Germany, 6-10 March, 2006.


Workshops with Informal Proceedings and Other Publications:

[4] Antonino Tumeo, Francesco Regazzoni, Marco Ceriani, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto,  Prototyping of Embedded Multiprocessor Architectures using the CerberO Framework, in 2nd Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Grenoble, France 18 March, 2011.

[3] Satish Chandra, Francesco Regazzoni, Marcello Lajolo, Hardware/Software Co-Design of an Operating Systems, in Work in Progress Session of 18th ECRTS, Dresden, Germany, 5-7 July, 2006.

[2] Francesco Regazzoni and Marcello Lajolo, HW/SW Partitioning and Interface Synthesis in NoCs, in Workshop on Future Interconnects and Network on Chips (NoC 2006), Munich, Germany, 10, 2006.

[1] Mariagiovanna Sami, Marco Macchetti, and Francesco Regazzoni, Speeding Security on the Intel StrongARM, in Embedded Intel Solutions, pages 31-33, Summer 2005.