Patents, Publications, Tutorials and Invited Seminars

Home Publications Projects

Patents:

 
P2 Inventors: Nele Mentens, Edoardo Charbon, Francesco Regazzoni, “Reconfigurable Logic Circuit”, Application Number: PCT/EP2018/081673, 19 November 2018 (Pending).
P1 Inventors: Andre Costi Nacul, Francesco Regazzoni, and Marcello Lajolo, Assignee: NEC Laboratories America, Inc. (Princeton, NJ), “Hardware scheduled SMP architectures”, Application Number: 11/947278, United States patent number: 7,502,378, Filed: 11 November, 2007, Issue date: 5 June, 2008.


Books and Book Chapters in Books with an Editorial Board:

Books
B2 Guido Marco Bertoni and Francesco Regazzoni, “Constructive Side-Channel Analysis and Secure Design - 11th International Workshop, COSADE 2020, Lugano, Switzerland, April 1-3, 2020, Revised Selected Papers, Lecture Notes in Computer Science 12244, Springer 2021.
B1 Nicolas Sklavos, Ricardo Chaves, Giorgio Di Natale, and Francesco Regazzoni, “Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, Springer, 2017.
Books Chapters
BC6 Paolo Palmieri, Ilia Polian and Francesco Regazzoni, “Security in an Approximated World: New Threats and Opportunities in the Approximate Computing Paradigm”, in Approximate Computing Techniques: From Component- to Application-Level, Editors: Alberto Bosio, Daniel Ménard, Olivier Sentieys, Springer, (to appear).
BC5 Christian Pilato, Donatella Sciuto, Francesco Regazzoni, Siddharth Garg and Ramesh Karri, “Protecting Hardware IP Cores during High-Level Synthesis”, in Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment Editors: Srinivas Katkoori and Sheikh Ariful Islam, Springer, (To Appear).
BC4 Roberta Piscitelli, Shivam Bhasin, and Francesco Regazzoni, “Fault Attacks, Injection Techniques and Tools for Simulation”, in Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, Springer, 2017.
BC3 Jelena Milosevic, Francesco Regazzoni, and Miroslaw Malek, “Malware Threats and Solutions for Trustworthy Mobile Systems Design”, in Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, Springer, 2017.
BC2 François Durvaux, Stéphanie Kerckhof, Francesco Regazzoni, and François-Xavier Standaert, “A Survey of Recent Results in FPGA Security and Intellectual Property Protection”, in Secure Smart Embedded Devices Platform and Applications, Editors: Konstantinos Markantonakis and Keith Mayes, Springer, 2014.
BC1 Francesco Regazzoni, Luca Breveglieri, Paolo Ienne, and Israel Koren, “Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks”, in Fault Analysis in Cryptography, Editors: Marc Joye and Michael Tunstall, Information Security and Cryptography Series, Springer, 2012.

Journals:

 
J22 Si Gao, Johann Großschädl, Ben Marshall, Dan Page, Thinh Pham, and Francesco Regazzoni, “An Instruction Set Extension to Support Software-Based Masking”, IACR Transactions on Cryptographic Hardware and Embedded Systems, Volume 2021, 2021.
J21 James Howe, Marco Martinoli, Elisabeth Oswald and Francesco Regazzoni, “Exploring Parallelism to Improve the Performance of FrodoKEM in Hardware”, Journal of Cryptographic Engineering, 2021.
J20 Francesco Regazzoni, Paolo Palmieri, Fethulah Smailbegovic, Rosario Cammarota, and Ilia Polian “Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning”, CAAI Transactions on Intelligence Technology, Volume 6, No. 2, Pages 180-191, 2021.
J19 Subhadeep Banik, Fatih Balli, Francesco Regazzoni, and Serge Vaudenay, “Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers”, IACR Transactions on Symmetric Cryptology, Volume 2020, No. 1, Pages 185-232, 2020.
J18 Sujit Rokka Chhetri, Anomadarshi Barua, Sina Faezi, Francesco Regazzoni, Arquimedes Canedo, and Mohammad Abdullah Al Faruque, “Tool of Spies: Leaking your IP by Altering the 3D Printer Compiler”, IEEE Transactions on Dependable and Secure Computing, (accepted in 2019, to appear).
J17 Stjepan Picek, Annelie Heuser, Alan Jovic, Shivam Bhasin, and Francesco Regazzoni, “The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations”, IACR Transactions on Cryptographic Hardware and Embedded Systems, Volume 2019, No. 1, Pages 209-237, 2019.
J16 Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri, “ Black-Hat High-Level Synthesis: Myth or Reality?”, IEEE Transactions on Very Large Scale Integration, 2018.
J15 Hamid Nejatollahi, Nikil Dutt, Sandip Ray, Francesco Regazzoni, Indranil Banerjee, Rosario Cammarota, “Post-quantum Lattice-based Cryptography Implementations: A Survey”, ACM Computing Surveys (CSUR), (accepted in 2018, to appear).
J14 Subhadeep Banik, Vasily Mikhalev, Frederik Armknecht, Takanori Isobe, Willi Meier, Andrey Bogdanov, Yuhei Watanabe, and Francesco Regazzoni, “Towards Low Energy Stream Ciphers”, IACR Transactions on Symmetric Cryptology, Volume 2018, No. 2, Pages 1-19, 2018.
J13 Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, and Francesco Regazzoni, “TaintHLS: A High-Level Synthesis Approach to Dynamic Information Flow Tracking in Hardware Accelerators”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.
J12 Debapriya Basu Roy, Manaar Alam, Sarani Bhattacharya, Vidya Govindan, Francesco Regazzoni, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, “Customized Instructions for Protection Against Memory Integrity Attacks”, IEEE Embedded Systems Letters, Volume 10, No. 3, Pages 91-94, 2018.
J11 Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, and Francesco Regazzoni, “Securing Hardware Accelerators: a New Challenge for High-Level Synthesis (Perspective Paper)”, IEEE Embedded Systems Letters, Volume 10, No. 3, Pages 77-80, 2018.
J10 Subhadeep Banik, Andrey Bogdanov, and Francesco Regazzoni, “Compact Circuits for Combined AES Encryption/Decryption”, Journal of Cryptographic Engineering, 2017.
J9 James Howe, Ayesha Khalid, Ciara Rafferty, Francesco Regazzoni, and Maire O'Neill, “On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography”, IEEE Transactions on Computers, Volume 67, No. 3, Pages 322-334, 2018.
J8 Mariagiovanna Sami, Miroslaw Malek, Umberto Bondi, and Francesco Regazzoni, “Embedded Systems Education: Job Market Expectations”, ACM SIGBED Review, Volume 14, No. 1, October 2016.
J7 Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, and Paolo Ienne, “Automatic Application of Power Analysis Countermeasures, IEEE Transactions on Computers Volume 64, No. 2, Pages 329-341, February 2015.
J6 Samuel Burri, Yuki Maruyama, Xavier Michalet, Francesco Regazzoni, Claudio Bruschini, and Edoardo Charbon, “Architecture and Applications of a High Resolution Gated SPAD Image Sensor”, Optics Express, Volume 22, No. 14, Pages 17573-17589, July 2014.
J5 Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, and Israel Koren, “A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks”, in IEEE Transactions on Emerging Topics Computing, Volume 2 No. 2: Pages 107-118, June 2014.
J4 Georg T. Becker, Francesco Regazzoni, Christof Paar, Wayne P. Burleson, “Stealthy dopant-level hardware Trojans: extended version. in Journal of Cryptographic Engineering, Volume 4, Issue 1 (2014), Pages 19-31 Springer.
J3 David Bol, Cédric Hocquet, and Francesco Regazzoni, “A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints”, in IEEE Transactions on Circuits and Systems II, Volume 59, No. 12, Pages 947-951, December 2012.
J2 Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, and François-Xavier Standaert, “Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags”, in Journal of Cryptographic Engineering, Volume 1, Issue 1 (2011), Pages 79-86, Springer.
J1 Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank Gurkaynak, Marco Macchetti, Zeynep Toprak, Laura Pozzi, Christof Paar, Yusuf Leblebici, and Paolo Ienne “Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology”, In Springer Transactions on Computational Science, Volume 5430, Pages 230-243, February 2009.

Conference Papers:

 
C103 Madura A. Shelton, Niels Samwel, Lejla Batina, Francesco Regazzoni, and Markus Wagner, “Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers”, in Proceedings of Network and Distributed System Security Symposium (NDSS 2021), virtual event, 21-24 February 2021.
C102 Radim Cmarx, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovick, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni, Katerina Slaninovak, Christoph Hagleitner, “EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms”, in Proceedings of Design, Automation and Test in Europe (DATE) 2021, virtual event, 1-5 February 2021.
C101 Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, and Mirjana Stojilovic, “Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks”, in Proceedings of Design, Automation and Test in Europe (DATE) 2021, virtual event, 1-5 February 2021 (Invited).
C100 Andrea Caforio, Fatih Balli, Subhadeep Banik, and Francesco Regazzoni, “A Deeper Look at the Energy Consumption of Lightweight Block Ciphers”, in Proceedings of Design, Automation and Test in Europe (DATE) 2021, virtual event, 1-5 February 2021 (Invited).
C99 Francesco Regazzoni, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena Ioana Vatajelu, and Ville Yli-Mäyry, “Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-”, in Proceedings of 39th International Conference on Computer-Aided Design, ICCAD 2020, San Diego, California, USA, 2-5 November 2020 (Invited).
C98 Giorgio Di Natale, Francesco Regazzoni, Vincent Albanese, Frank Lhermet, Yann Loisel, Abderrahmane Sensaoui, and Samuel Pagliarini, “Latest Trends in Hardware Security and Privacy”, in Proceedings of 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 20), Frascati, Italy, 19-21 October, 2020 (Invited).
C97 Claudio Bareato, Paolo Palmieri, Francesco Regazzoni and Oreste Venier, “A secure, distributed and scalable infrastructure for remote generation and use of cryptographic keys”, in Proceedings of 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services (BRAINS), Paris, France, 28-30 September 2020.
C96 Francesco Regazzoni and Ilia Polian, “Side Channel Attacks vs Approximate Computing”, in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) 2020, virtual event, China, 7-9 September 2020 (Invited).
C95 Huili Chen, Rosario Cammarota, Farinaz Koushanfar, Felipe Valencia, and Francesco Regazzoni, “AHEC: End-To-End Compiler Framework for Privacy-Preserving Machine Learning Acceleration”, in Proceedings of 57th Design Automation Conference (DAC) 2020, San Francisco, California, USA, 20-24 July 2020.
C94 Terry Simon, Lejla Batina, Joan Daemen, Vincent Grosso, Pedro Maat Costa Massolino, Kostas Papagiannopoulos, Francesco Regazzoni, and Niels Samwel, “Friet: An Authenticated Encryption Scheme with Built-in Fault Detection”, in Proceedings of 39th Annual International Conference on the Theory and Applications of Cryptographic Techniques (EUROCRYPT 2020), Zagreb, Croatia, 10-14 May 2020.
C93 Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont, Ilia Polian, “Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA”, in Proceedings of Proceedings of Design, Automation and Test in Europe (DATE) 2020, Grenoble, France, 9-13 March 2020 (Invited).
C92 Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, and Mirjana Stojilovic, “Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?”, in Proceedings of Design, Automation and Test in Europe (DATE) 2020, Grenoble, France, 9-13 March 2020.
C91 Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, and Mirjana Stojilovic, “Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs”, in Proceedings of International Symposium on Field-Programmable Gate Arrays (FPGA) 2020, Monterey, CA, USA, 23-25 February 2020.
C90 Huili Chen, Rosario Cammarota, Felipe Valencia, and Francesco Regazzoni, “PlaidML-HE: Acceleration of Deep Learning Kernels to Compute on Encrypted Data”, in Proceedings of IEEE International Conference on Computer Design (ICCD) 2019, Abu Dhabi, United Arab Emirates, 17-20 November 2019 (Invited).
C89 Felipe Valencia, Ilia Polian, and Francesco Regazzoni, “Fault Sensitivity Analysis of Lattice-based Post-Quantum Cryptographic Components”, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC) 2019, Samos, Greece, 7-11 July 2018 (Accepted, to appear).
C87 James Howe, Marco Martinoli, Ayesha Khalid, Francesco Regazzoni, and Elisabeth Oswald, “Fault Attack Countermeasures for Error Samplers in Lattice-Based Cryptography”, IEEE International Symposium on Circuits and Systems (ISCAS) 2019, Sapporo, Japan, 26-29 May 2019.
C86 Stefan Katzenbeisser, Ilia Polian, Francesco Regazzoni, and Marc Stöttinger, “Security in Autonomous Systems, IEEE European Test Symposium (ETS) 2019, Baden-Baden, Germany, 27-31 May 2019.
C85 Christian Pilato, Kanad Basu, Mohammed Shayan, Francesco Regazzoni, and Ramesh Karri, “High-Level Synthesis of Benevolent Trojans”, Design, Automation and Test in Europe (DATE) 2019, Florence, Italy, 25-29 March 2019.
C84 Muhammad Abdul Wahab, Jelena Milosevic, Francesco Regazzoni and Alberto Ferrante, “Power and performance optimized hardware classifiers for efficient on-device malware detection”, CS2@HiPEAC 2018, Valencia, Spain, 21 January 2019.
C83 Francesco Regazzoni, Cesare Alippi, and Ilia Polian, “Security: the dark side of approximate computing?, in Proceedings of 37th International Conference on Computer-Aided Design, ICCAD 2018, San Diego, California, USA, 5-8 November 2018 (Invited).
C82 Francesco Regazzoni, AustinFowler, and Ilia Polian, “Quantum era challenges for classical computer”, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC) 2018, Samos, Greece, 15-19 July 2018 (Invited).
C81 Christian Pilato, Francesco Regazzoni, Ramesh Karri, and Siddharth Garg, “TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis”, in Proceedings of 55th Design Automation Conference (DAC) 2018, San Francisco, California, USA, 24-28 June 2018.
C80 Ayesha Khalid, James Howe, Ciara Rafferty, Francesco Regazzoni, and Maire O'Neil, “Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography”, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, 27-30 May, 2018.
C79 Ayesha Khalid, Tobias Oder, Felipe Valencia, Máire O'Neill, Tim Güneysu, Francesco Regazzoni, “Physical Protection of Lattice-Based Cryptography: Challenges and Solutions”, in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) 2018, Chicago, IL (U.S.A.), 23-25 May 2018 (Invited).
C78 Ricardo Chaves, Lukasz Chmielewski, Francesco Regazzoni and Lejla Batina, “SCA-resistance for AES: How cheap can we go?”, 1Oth International Conference on Cryptology - Africacrypt 2018, Marrakesh, Morocco, 7-9 May, 2018.
C77 Subhadeep Banik, Andrey Bogdanov, Takanori Isobe, Harunaga Hiwatari, Toru Akishita, and Francesco Regazzoni, “Inverse Gating for Low Energy Block Ciphers”, in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2018, Washington DC, USA, 30 April - 4 May, 2018.
C76 Nele Mentens, Edoardo Charbon, and Francesco Regazzoni, “Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow”, in Proceedings of FCCM, Boulder, Colorado, Manchester, USA, 29 April - 2 May, 2018.
C75 Felipe Valencia, Tobias Oder, Tim Güneysu, and Francesco Regazzoni, “Exploring the Vulnerability of R-LWE Encryption to Fault Attacks”, in Proceedings of CS2@HiPEAC 2018, Manchester, United Kingdom, 24 January, 2018.
C74 Elizabeth O'Sullivan and Francesco Regazzoni, “Special Session Paper: Efficient Arithmetic for lattice-based Cryptography”, in Proceedings of CODES+ISSS 2017, Seoul, South Korea, 15-20 October, 2017 (Invited).
C73 Felipe Valencia, Ayesha Khalid, Elizabeth O'Sullivan, and Francesco Regazzoni “The Design Space of the Number Theoretic Transform: a Survey”, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC) 2017, Samos, Greece, 17-20 July 2017 (Invited)
C72 Ilia Polian and Francesco Regazzoni, “Counteracting malicious faults in cryptographic circuits”, in Proceedings of IEEE European Test Symposium (ETS) 2017, Limassol, Cyprus, 22-26 May, 2017.
C71 Subhadeep Banik, Andrey Bogdanov, and Francesco Regazzoni, “Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths”, in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, McLean, VA, USA, 1-5 May 2017.
C70 Michael Masin, Francesca Palumbo, Hans Myrhaug, Julio A. de Oliveira Filho, Max Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, Angel A. Sanchez, Antonella Toffetti, Eduardo de la Torre, and Katiuscia Zedda, “Cross-layer Design of Reconfigurable Cyber-Physical Systems”, in Proceedings of Design, Automation and Test in Europe (DATE) 2017, Lausanne, Switzerland, 27-31 March 2017.
C69 Francesco Regazzoni and Ilia Polian, “Securing the Hardware of Cyber-Physical Systems”, in Proceedings of 22th Asia and South Pacific Design Automation Conference (ASP-DAC) 2017, Chiba, Japan, 16 - 19 January, 2017 (Invited).
C68 Tobias Oder, Tim Güneysu, Felipe Valencia, Ayesha Khalid, Maire O'Neill, Francesco Regazzoni, “Lattice-Based Cryptography: from Reconfigurable Hardware to ASIC”, in Proceedings of International Symposium on Integrated Circuits (ISIC) 2016, Singapore, Singapore, 12-14 December 2016 (Invited).
C67 Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, “Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core”, in Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016, Kolkata, India, 11-14 December 2016.
C66 Ilia Polian, Georg T Becker, and Francesco Regazzoni, “Trojans in Early Design Steps - An Emerging Threat”, in Proceedings of TRUDEVICE Final Conference (FCTRU'16), Barcelona, Spain, 14-16 November 2016.
C65 Francesco Regazzoni, “Physical Attacks and Beyond”, in Proceedings of Selected Areas in Cryptography: 23nd International Conference (SAC) 2016, BSt. John's, Newfoundland and Labrador, Canada,10-12 August 2016.
C64 Sebastien Bellon, Claudio Favi, Marco Macchetti, Miroslaw Malek and Francesco Regazzoni, “Evaluating Physically Unclonable Functions on a large set of FPGAs”, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC) 2016, Samos, Greece, 18-21 July 2016.
C63 James Howe, Ciara Moore, Maire O'Neill, Francesco Regazzoni, Tim Güneysu, Kevin Beeden, “Standard Lattices in Hardware”, in Proceedings of 53th Design Automation Conference (DAC) 2016, Austin, Texas, USA, 5-9 June 2016.
C62 Subhadeep Banik, Andrey Bogdanov, Tiziana Fanni, Carlo Sau, Luigi Raffo, Francesca Palumbo, and Francesco Regazzoni, “Adaptable AES implementation with power-gating support”in Proceedings of ACM International Conference on Computing Frontiers (CF) 2016, Como, Italy, 16-18 May 2016.
C61 Maire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafael Del Pino, Michel Abdalla, Francesco Regazzoni, Andres Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, Bassem, and David David, “Secure architectures of future emerging cryptography”, in Proceedings of ACM International Conference on Computing Frontiers (CF) 2016, Como, Italy, 16-18 May 2016 (Invited).
C60 Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, Takanori Isobe, Harunaga Hiwatari, and Toru Akishita, “Round gating for low energy block ciphers”, in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2016, McLean, VA, USA, 3-5 May 2015.
C59 Francesco Regazzoni and Paolo Ienne, “Instruction Set Extensions for secure applications”, in Proceedings of Design, Automation and Test in Europe (DATE) 2016, Dresden, Germany, 14-18 March 2016 (Invited).
C58 Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, and Francesco Regazzoni, “Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only)”, in Proceedings of International Symposium on Field-Programmable Gate Arrays (FPGA) 2016, Monterey, CA, USA, 21-23 February 2016.
C57 Subhadeep Banik, Andrey Bogdanov, and Francesco Regazzoni, “Exploring the energy consumption of lightweight blockciphers in FPGA, in Proceedings of International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Cancun, Mexico, 8-10 December, 2015.
C56 Subhadeep Banik, Andrey Bogdanov, Takanori Isobe, Kyoji Shibutani, Harunaga Hiwatari, Toru Akishita, and Francesco Regazzoni, “Midori: A Block Cipher for Low Energy”, in Proceedings of 21st International Conference on the Theory and Application of Cryptology and Information Security (ASIACRYPT) 2015, Auckland, New Zealand, 29 November - 3 December 2015.
C55 Mohammad Abdullah Al Faruque, Francesco Regazzoni, Miroslav Pajic, “Design methodologies for securing cyber-physical systems”, in Proceedings of (CODES+ISSS) 2015. Amsterdam, The Netherlands, 4-9 October 2015 (Invited).
C54 Subhadeep Banik, Andrey Bogdanov, and Francesco Regazzoni, “Exploring Energy Efficiency of Lightweight Block Ciphers”, in Proceedings of Selected Areas in Cryptography: 22nd International Conference (SAC) 2015, Sackville, NB, Canada, 12-14 August 2015.
C53 Shivam Bhasin and Francesco Regazzoni, “A survey on hardware trojan detection techniques”, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, 24-27 May 2015 (Invited).
C52 Ricardo Chaves, Giorgio Di Natale, Lejla Batina, Shivam Bhasin, Baris Ege, Apostolos Fournaris, Nele Mentens, Stjepan Picek, Francesco Regazzoni, Vladimir Rozic, Nicolas Sklavos, Bohan Yang, “Challenges in designing trustworthy cryptographic co-processors”, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, 24-27 May 2015 (Invited).
C51 Jelena Milosevic, Alberto Ferrante, and Francesco Regazzoni, “Security Challenges for Hardware Designers of Mobile Systems”, in Proceedings of Mobile Systems Technologies Workshop (MST) 2015, Milan, Italy, 22 May 2015 (Invited).
C50 Roberta Piscitelli, Shivam Bhasin, and Francesco Regazzoni, “Fault attacks, injection techniques and tools for simulation”, in Proceedings of 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS) 2015, Naples, Italy, 21-23 April 2015 (Invited).
C49 Xiaofei Guo, Nagmeh Karimi, Francesco Regazzoni, Chenglu Jin, and Ramesh Karri, “Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks”, in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2015, McLean, VA, USA, 5-7 May 2015.
C48 Harald Homulle, Francesco Regazzoni, Edoardo Charbon “200 MS/s ADC implemented in a FPGA employing TDCs”, in Proceedings of International Symposium on Field-Programmable Gate Arrays (FPGA) 2015, Monterey, CA, USA, 22-24 February 2015.
C47 Cesare Alippi, Andrey Bogdanov, and Francesco Regazzoni, “Lightweight cryptography for constrained devices”, in Proceedings of International Symposium on Integrated Circuits (ISIC) 2014, Singapore, Singapore, 10-12 December 2014 (Invited).
C46 João Amaral, Francesco Regazzoni, Pedro Tomás, and Ricardo Chaves:, “Accelerating differential power analysis on heterogeneous systems”, in Proceedings of 9th Workshop on Embedded Systems Security (WESS) 2014, New Delhi, India, 17 October 2014.
C45 Mariagiovanna Sami, Miroslaw Malek, Umberto Bondi, and Francesco Regazzoni, “Embedded Systems Education: Job Market Expectations”, in Proceedings of Workshop on Embedded and Cyber-Physical Systems Education (WESE) 2014, New Delhi, India, 16 October 2014.
C44 Tim Güneysu, Francesco Regazzoni, Pascal Sasdrich, and Marcin Wojcik, “THOR - The hardware onion router”, in Proceedings of International Conference on Field Programmable Logic and Applications(FPL) 2014, Munich, Germany, 2-4 September 2014. .
C43 Shivam Bhasin, Paolo Maistri, and Francesco Regazzoni, “Malicious wave: A survey on actively tampering using electromagnetic glitch”, in Proceedings of International Symposium on Electromagnetic Compatibility (EMC) 2014, Tokyo, Japan, 12-16 May 2014 (Invited).
C42 Samuel Burri, François Powolny, Claudio Bruschini, Xavier Michalet, Francesco Regazzoni, and Edoardo Charbon, “A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging”, in Proceedings of SPIE Photonics Europe, Brussels, Belgium, 14-17 April 2014 .
C41 Samuel Burri, Damien Stucki, Yuki Maruyama, Claudio Bruschini, Edoardo Charbon, Francesco Regazzoni, “SPADs for Quantum Random Number Generators and beyond”, in Proceedings of 19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, Singapore, Singapore, 20-23 January 2014 (Invited).
C40 M. Legré, Samuel Burri, Edoardo Charbon, Christopher J. Chunnilall, Daniela Frauchiger, Raphael Houlmann, Alessio Meneghetti, Francesco Regazzoni, Renato Renner, Damien Stucki, Matthias Troyer, Hugo Zbinden, Towards a High Quality and High Speed QRNG“, in Proceedings of Single Photon Workshop (SPW) 2013, Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA, 15-18 October 2013 (Invited).
C39 Damien Stucki, Samuel Burri, Edoardo Charbon, Christopher J. Chunnilall, Alessio Meneghetti, and Francesco Regazzoni, “Towards a High-speed Quantum Number Generator”, in Proceedings of SPIE Security Defence, Dresden, Germany, 23-26 September 2013.
C38 Ali Galip Bayrak, Francesco Regazzoni, David Novo Bruna, Paolo Ienne, ”Sleuth: Automated Verification of Software Power Analysis Countermeasures”, in Proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES) 2013, Santa Barbara, California, USA, 18-22 August 2013.
C37 Georg Becker, Francesco Regazzoni, Christof Paar, and Wayne Burleson, ”Stealthy Dopant-Level Hardware Trojans”, in Proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES) 2013, Santa Barbara, California, USA, 18-22 August 2013.
C36 François Powolny, Samuel Burri, Claudio Bruschini, Xavier Michalet, Francesco Regazzoni and Edoardo Charbon, “Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution”, in Proceedings of International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, 12-16 June 2013.
C35 Burri, Samuel, Damien Stucki, Yuki Maruyama, Claudio Bruschini, Edoardo Charbon, and Francesco Regazzoni, “Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator”, in Proceedings of International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, 12-16 June 2013.
C34 Edoardo Charbon and Francesco Regazzoni, “Single-photon image sensors”, in Proceedings of 50th Design Automation Conference (DAC) 2013, Austin, Texas, USA, 2-6 June 2013 (Invited).
C33 Venkataraman Krishnaswami, Samuel Burri, Francesco Regazzoni, Claudio Bruschini, Cornelis J. F. van Noorden, Edoardo Charbon, and Ron Hoebe “SPAD array camera for localization based super resolution microscopy”, Proceedings of Focus on Microscopy (FOM) 2013, Maastricht, The Netherlands, 24-27 March 2013.
C32 Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo Bruna, Philip Brisk, and Paolo Ienne, “An eda-friendly protection scheme against side-channel attacks”, in Proceedings of Design, Automation and Test in Europe (DATE) 2013, Grenoble, France, 18-22 March 2013.
C31 Andrey Bogdanov, Florian Mendel, Francesco Regazzoni, Vincent Rijmen and Elmar Tischhauser, “ALE: AES-Based Lightweight Authenticated Encryption”, in Proceedings of Fast Software Encryption (FSE), Singapore, Singapore, 10-13 March 2013.
C30 Josep Balasch, Baris Ege, Thomas Eisenbarth, Benoît Gérard, Zheng Gong, Tim Güneysu, Stefan Heyse, Stéphanie Kerckhof, Francois Koeune, Thomas Plos, Thomas Poppelmann, Francesco Regazzoni, Francois-Xavier Standaert, Gilles Van Assche, Ronny Van Keer, Loic Van Oldeneel Tot Oldenzeel and Ingo von Maurich, “Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices”, in Proceedings of 11th Smart Card Research and Advanced Application Conference (CARDIS) 2012, Graz, Austria, 28-30 November 2012.
C29 Alessandro Barenghi, Gerardo Pelosi, Francesco Regazzoni, “Simulation-Time Security Margin Assessment against power-based Side Channel Attacks”, in Proceedings of 7th Workshop on Embedded Systems Security (WESS) 2012, Tampere, Finland, 11 October 2012.
C28 Thomas Eisenbarth, Zheng Gong, Tim Güneysu, Stefan Heyse, Sebastiaan Indesteege, Stéphanie Kerckhof, François Koeune, Tomislav Nad, Thomas Plos, Francesco Regazzoni, François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, “Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices”, in Proceedings of Progress in Cryptology - Africacrypt 2012, Ifrane, Morocco, 10-12 July, 2012.
C27 Leandro Fiorin, Alberto Ferrante, Kostantinos Padarnitas, and Francesco Regazzoni, “Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation”, in Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC) 2012, Sydney, Australia, 30 January - 2 February 2012.
C26 Bishal Lamichhane, Steven Mudda, Francesco Regazzoni, Alessandro Puiatti: “LEXCOMM: A low energy, secure and flexible communication protocol for a heterogenous body sensor network”, in Proceedings of IEEE-EMBS International Conference on Biomedical and Health Informatics 2012, Hong Kong, China, 5-7 January 2012.
C25 Marcel Medwed, Christophe Petit, Francesco Regazzoni, Mathieu Renauld, and François-Xavier Standaert, “Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks”, In Proceedings of 10th Smart Card Research and Advanced Application Conference (CARDIS) 2011, Leuven, Belgium, 14-16 September 2011.
C24 Stéphanie Kerckhof, François Durvaux, Nicolas Veyrat-Charvillon, Francesco Regazzoni, Guerric Meurice de Dormale, and François-Xavier Standaert, “Low Cost FPGA Implementations of the SHA-3 Finalists”, In Proceedings of 10th Smart Card Research and Advanced Application Conference (CARDIS) 2011, Leuven, Belgium, 14-16 September 2011.
C23 Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, and Israel Koren, “Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation”, In Proceedings of 7th Workshop on RFID Security and Privacy (RFIDSec) 2011, Amherst, Massachussets, USA, 26-28 June 2011.
C22 Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, and Paolo Ienne, “A First Step Towards Automatic Application of Power Analysis Countermeasures”, in Proceedings of 48th Design Automation Conference (DAC) 2011, San Diego, Califorina, 5-9 June 2011 (HiPEAC paper award).
C21 Alessandro Cevrero, Francesco Regazzoni, Michael Schwander, Stéphane Badel, Paolo Ienne, and Yususf Leblebici “Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library”, in Proceedings of 48th Design Automation Conference (DAC) 2011, San Diego, Califorina, 5-9 June 2011 (HiPEAC paper award).
C20 Francesco Regazzoni, Wang Yi, and François-Xavier Standaert “FPGA Implementations of the AES Masked Against Power Analysis Attacks”, in Proceedings of 2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE) 2011, Darmstadt, Germany, 24-25 February 2011.
C19 Jean-Francois Gallais, Johann Großschädl, Neil Hanley, Markus Kasper, Marcel Medwed, Francesco Regazzoni, Joern-Marc Schmidt, Stefan Tillich, and Marcin Wojcik “Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software”, in Proceedings of 2nd International Conference on Trusted Systems, (INTRUST) 2010, Beijing, China, 13-15 December 2010.
C18 Alessandro Barenghi, Luca Breveglieri, Israel Koren, Gerardo Pelosi, and Francesco Regazzoni “Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs”, in Proceedings of 5th Workshop on Embedded Systems Security (WESS) 2010, Scottsdale, Arizona, USA, 24 October 2010.
C17 Marcel Medwed, François-Xavier Standaert, Johann Großschädl, and Francesco Regazzoni, “Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices”, in Proceedings of Progress in Cryptology - Africacrypt 2010, Stellenbosch, South Africa, 3-6 May 2010.
C16 Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. “A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation”, in Proceedings of Design, Automation and Test in Europe (DATE) 2010, Dresden, Germany, 6-12 March 2010.
C15 Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier van Damme, Giacomo de Meulenaer, Junfeng Fan, Frank Gurkaynak, Tim Güneysu, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, and Leif Uhsadel. “The Certicom Challenges ECC2-X”, in Proceedings of Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS'09), Lausanne (Switzerland), 9-10 September 2009.
C14 Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, and Paolo Ienne. “A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions”, in Proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), Lausanne (Switzerland), 6-9 September 2009.
C13 Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, and Israel Koren, “Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?”, in Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), Cambridge, MA, USA, 1-3 October, 2008.
C12 Guido Marco Bertoni, Luca Breveglieri, Roberto Farina, and Francesco Regazzoni, “A 640 Mbit/s 32-bit pipelined implementation of the AES algorithm”, in Proceedings of International Conference on Security and Cryptography SECRYPT 2008, Porto, Portugal, 26-29 July 2008.
C11 Joao Otero, Francesco Regazzoni and Marcello Lajolo, “Rapid Creation of Application Models from Bandwidth Aware Core Graphs”, in Proceedings of IP Based SoC Design 2007, Grenoble, France, 5-6 December 2007.
C10 Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren and Christof Paar “Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits”, in Proceedings of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 07), Rome, Italy, 26-28 September 2007.
C9 Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici and Paolo Ienne “Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies”, in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC) 2007, Samos, Greece, 16-19 July 2007.
C8 Francesco Regazzoni, Ivano Bonesana, Maksim Djakov, and Amanda Mattiuz “Tairona, an Open Source Platform for On-Line Meeting and Tutoring”, in Proceedings of World Conference on Educational Multimedia, Hypermedia and Telecommunications (ED-MEDIA 07), Vancouver, Canada, 25-29 June 2007.
C7 Andre Costi Nacul, Francesco Regazzoni, and Marcello Lajolo “Hardware Scheduling Support in SMP Architectures”, in Proceedings of Design, Automation and Test in Europe (DATE) 2007, Nice, France, 16-20 April 2007.
C6 Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, and Kai Schramm “Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes”, in Proceedings of IEEE International Conference on VLSI Design & Embedded Systems, Bangalore, India, 6-10 January 2007.
C5 Guido Marco Bertoni, Luca Breveglieri, Roberto Farina and Francesco Regazzoni, “Speeding Up AES By Extending a 32 bit Processor Instruction Set”, in Proceedings of International Conference on Application-specific Systems, Architectures and Processors (ASAP 2006), Steamboat Springs, Colorado, USA, 11-13 September 2006.
C4 Satish Chandra, Francesco Regazzoni, Marcello Lajolo, “Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach”, in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) 2006, Philadelphia, PA (U.S.A.), 30 April - 2 May 2006.
C3 Francesco Regazzoni and Marcello Lajolo, “Hardware/Software Partitioning and Interface Synthesis in Networks On Chip”, in Proceedings of IP Based SoC Design 2005, Grenoble, France, December 7-8, 2005.
C2 Francesco Regazzoni, Andre Costi Nacul, and Marcello Lajolo, “Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures”, in Proceedings of FDL'05 - Forum on Specification and Design Languages. Lausanne, Switzerland, 27-30 September 2005.
C1 Francesco Regazzoni and Marcello Lajolo, “Interface Synthesis in Multiprocessing Systems-On-Chips”, in Proceedings of IP Based SoC Design 2004, Grenoble, France, 8-9 December 2004.

Other Publications and Pre-Prints:

 
I31 Subhadeep Banik, Francesco Regazzoni, and Serge Vaudenay:”Lightweight Circuits with Shift and Swap”, available on IACR Cryptology ePrint Archive, 1114 (2018).
I30 Thierry Simon, Lejla Batina, Joan Daemen, Vincent Grosso, Pedro Maat Costa Massolino, Kostas Papagiannopoulos, Francesco Regazzoni, Niels Samwel: ”Towards Lightweight Cryptographic Primitives with Built-in Fault-Detection”, available on IACR Cryptology ePrint Archive, 729 (2018).
I29 Nele Mentens, Edoardo Charbon, Francesco Regazzoni ”Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow”, available on IACR Cryptology ePrint Archive, 724 (2018).
I28 Stjepan Picek, Annelie Heuser, Alan Jovic, Shivam Bhasin, and Francesco Regazzoni, ”The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations ”, available on IACR Cryptology ePrint Archive, 476 (2018).
I27 Ayesha Khalid, James Howe, Ciara Rafferty, Francesco Regazzoni, and Maire O'Neill, ”Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography”, available on IACR Cryptology ePrint Archive, 265 (2018).
I26 Francesco Regazzoni, ”Automatic Application of Side Channel Countermeasures: History and Perspectives”, in TRUDEVICE Workshop, Dresden, Germany, 23 March 2018.
I25 Séamus Brannigan, Neil Smyth, Tobias Oder, Felipe Valencia, Elizabeth O'Sullivan, Tim Güneysu, and Francesco Regazzoni, ”An Investigation of Sources of Randomness Within Discrete Gaussian Sampling”, available on IACR Cryptology ePrint Archive, 298 (2017).
I24 Maire O'Neill, Gavin McWilliams, Robert Griffin, Stephen Wray, David Lund, Tim Güneysu, Francesco Regazzoni, Elizabeth O'Sullivan, and Adrian Waller , ”Quantum Resistant Cryptography for Embedded Systems and IoT”, in Embedded World 2017, Nuremberg, Germany, 14 - 16 March 2017.
I23 Francesco Regazzoni, ”Integrating Security into Design Flows”, in Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS), Austin, Texas, USA, 10 November 2016.
I22 Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, ”Atomic-AES v 2.0”, available on IACR Cryptology ePrint Archive, 1005 (2016).
I21 Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, ”Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core”, available on IACR Cryptology ePrint Archive, 927 (2016).
I20 Philip Hodgers, Richard Gilmore, Ciara Moore, Markku Saarinen, Maire O'Neill, Tobias Oder, Tim Güneysu, Felipe Valencia, and Francesco Regazzoni , ”Physical Attacks Against Lattice Based Cryptography”, in 14th CryptArchi Workshop, La Grande Motte, France, 21 - 24 June 2016.
I19 Subhadeep Banik, Andrey Bogdanov, Takanori Isobe, Kyoji Shibutani, Harunaga Hiwatari, Toru Akishita, Francesco Regazzoni, ”Midori: A Block Cipher for Low Energy (Extended Version)”, available on IACR Cryptology ePrint Archive, 1142 (2015).
I18 Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, ”Exploring Energy Efficiency of Lightweight Block Ciphers”, available on IACR Cryptology ePrint Archive, 847 (2015).
I17 Joao Carlos C. Resende, Shivam Bhasin, Francesco Regazzoni, and Ricardo Chaves, ”One Core Fit All: Towards Merging block ciphers on FPGA”, in 13th CryptArchi Workshop, Leuven, Belgium, 28 June - 1st July 2015.
I16 Francesco Regazzoni, Andrey Bogdanov, Luca Breveglieri, and Israel Koren, ”Error Detection and Correction for Lightweight Cryptographic Algorithms”, in TRUDEVICE Workshop, Grenoble, France, 13 March 2015.
I15 Alessandro Barenghi, Gerardo Pelosi, Francesco Regazzoni, ”Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks”, available on IACR Cryptology ePrint Archive, 307 (2014).
I14 Francesco Regazzoni, ”High-Throughput Implementation of AES-Based Lightweight Authenticated Encryption - ALE”, in 11th CryptArchi Workshop, Fréjus, France, June 23rd-26th 2013.
I13 Josep Balasch, Baris Ege, Thomas Eisenbarth, Benoıt Gérard, Zheng Gong, Tim Güneysu, Stefan Heyse, Stéphanie Kerckhof, François Koeune, Thomas Plos, Thomas Pöppelmann, Francesco Regazzoni, François-Xavier Standaert, Gilles Van Assche, Ronny Van Keer, Loïc van Oldeneel tot Oldenzeel, Ingo von Maurich, ”Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices”, available on IACR Cryptology ePrint Archive, 507 (2012).
I12 Andrey Bogdanov, Florian Mendel, Francesco Regazzoni, Vincent Rijmen , ”Lightweight AES-Based Authenticated Encryption”, in ECRYPT II Workshop on Directions in Authenticated Ciphers (DIAC 2012), Stockholm, Sweden, 5-6 July 2012.
I11 Jardim Verdolin Dabreu Bruna, Francesco Regazzoni, and Antonino Tumeo, “Bitsliced implementation of the AES algorithm on GPU”, in 3nd Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany 16 March, 2012.
I10 Stéphanie Kerckhof, François Durvaux, Nicolas Veyrat-Charvillon, Francesco Regazzoni, Guerric Meurice de Dormale, and François-Xavier Standaert, ”Low Cost FPGA Implementations of the SHA-3 Finalists”, in ECRYPT II Hash Workshop, Tallin, Estonia, May 2011.
I9 Antonino Tumeo, Francesco Regazzoni, Marco Ceriani, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto, “Prototyping of Embedded Multiprocessor Architectures using the CerberI Framework”, in 2nd Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Grenoble, France 18 March, 2011.
I8 Daniel V. Bailey, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Hsieh-Chung Chen, Chen-Mou Cheng, Gauthier Van Damme, Giacomo de Meulenaer, Luis J. Dominguez Perez, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Ruben Niederhagen, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel, Anthony Van Herrewege, Bo-Yin Yang, ”Breaking ECC2K-130”, available on IACR Cryptology ePrint Archive, 541 (2009).
I7 Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier Van Damme, Giacomo de Meulenaer, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel, ”The Certicom Challenges ECC2-X”, available on IACR Cryptology ePrint Archive, 466 (2009).
I6 Francesco Regazzoni, “A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions”, University Booth demonstration at 46 Design Automation Conference (DAC), San Francisco, California, USA, July 26-31, 2009.
I5 Francesco Regazzoni, “Side Channel Resistant Design Flow”, PhD Forum at DATE 2008, Munich, Germany, March 10-14, 2008.
I4 Francesco Regazzoni, “DPA Resistant Design Flow”, University Booth demonstration at 44 Design Automation Conference (DAC), San Diego, California, USA, June 4-8, 2007.
I3 Satish Chandra, Francesco Regazzoni, Marcello Lajolo, “Hardware/Software Co-Design of an Operating Systems”, in Work in Progress Session, 18th ECRTS, Dresden, Germany, July 5 - July 7, 2006.
I2 Francesco Regazzoni and Marcello Lajolo, “HW/SW Partitioning and Interface Synthesis in NoCs”, in Workshop on Future Interconnects and Network on Chips (NoC 2006), Munich, Germany, 10, 2006.
I1 Mariagiovanna Sami, Marco Macchetti, and Francesco Regazzoni, “Speeding Security on the Intel StrongARM”, in Embedded Intel Solutions, pages 31-33, Summer 2005.

Tutorials and Invited Lectures

 
T17 “Towards the Automatic Application of Physical Attacks Countermeasures”, lecture at ASEC Summer School, Adelaide, Australia, 11 December 2018.
T16 “Cryptographic hardware engineering”, lecture at SAC Summer School (S3), Calgary, Canada, 14 August 2018.
T15 “Security Challenges in CPS”, tutorial at Cyber-Physical Systems Week, Porto, Portugal, 10 April 2018.
T14 “Towards the Automatic Application of Physical Attacks Countermeasures”, lecture at RISE Spring School, Cambridge, United Kingdom, 28 March 2018.
T13 “Securing CPSs, new challenge or solved problem?”, lecture at CPS Summer School 2017, Porto Conte, Italy, 28 October 2017.
T12 “Performance Metrics of Digital Design”, lecture at Summer School on Real-World Crypto and Privacy, Šibenik, Croatia, 6 June 2017.
T11 “Counteracting malicious faults in cryptographic circuits”, tutorial at IEEE European Test Symposium (ETS) 2017, Limassol, Cyprus, 24 May, 2017.
T10 “Side Channel Resistant Implementations of Post Quantum Cryptography”, tutorial QRC: Architectures and Software for Quantum Resistant Cryptography at High Performance and Embedded Architecture and Compilation (HiPEAC) 2017, Stockholm, Sweden, 25 January 2017.
T9 “Security Threats for Reconfigurable Hardware”, tutorial at International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland, 2 September 2016.
T8 “Secure Hardware Implementation of Symmetric Key Ciphers (Including Side Channel Resistance)”, lecture at SAC Summer School (S3), St. John's, Newfoundland and Labrador, Canada, 8 August 2016.
T7 “Introduction to Hardware Trojans”, lecture at TRUDEVICE Training School, Leukerbad, Switzerland, 21 April 2016.
T6 “Bricks and Tools for Side Channel Resistant Hardware”, tutorial at Working Groups Meeting, Cryptacus COST Action, Haifa, 30 March 2016.
T5 “Security Challenges at Hardware Design Time for mobile systems”, tutorial at HESES Workshop at the HIPEAC Conference, Prague, Czech Republic, 18 January 2016.
T4 “Towards the Automatic Applications of Side Channel Countermeasures”, lecture at IACR School on Design and Security of Cryptographic Algorithms and Devices, Chia, Italy, 23 October 2015.
T3 “Introduction to hardware design of block ciphers”, lecture at IACR School on Design and Security of Cryptographic Algorithms and Devices, Chia, Italy, 20 October 2015.
T2 “Physical attacks, introduction and application to embedded processors”, tutorial at 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS) 2015, Naples, Italy, 21 April 2015.
T1 “Bricks and Tools for Secure Hardware Implementations”, lecture at Summer School on Real-World Crypto and Privacy, Šibenik, Croatia, 6 June 2014.

Given Seminars

 
S47 “The earlier the better: explaining hardware and CPS security in high-schools”, seminar at European Workshop on Microelectronics Education, Braunschweig, Germany , 25 September 2018.
S46 “Design of quantum resistant cyber-physical systems and IoT devices”, seminar at International Verification and Security Workshop, Platja D'Aro, Spain, 4 July 2018.
S45 “Towards the Automatic Application of Physical Attacks Countermeasures”, seminar at Cryptography Research Rambus, San Francisco, California, USA, 26 June 2018.
S44 “Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow”, seminar at 11th CryptArchi Workshop, Guidel-Plages, France, 19 June 2018.
S43 “Fault Attack Resistance of Post Quantum Algorithms”, seminar at 11th CryptArchi Workshop, Guidel-Plages, France, 18 June 2018.
S42 “Towards efficient and physically secure lattice based cryptography”, seminar at University of California Riverside, Riverside, California, USA, 23 May 2018.
S41 “Quantum Computer and Cryptography: Threats, Challenges, and Opportunities”, seminar at Emertech, Singapore, Singapore, 25 April 2018.
S40 “Automatic Application of Side Channel Countermeasures: History and Perspectives”, seminar at Radboud University, Nijmegen, The Netherlands, 13 March 2018.
S39 “Exploring Fault Attacks Resistance and Possible Countermeasures for Lattice Based Cryptography”, seminar at 16th IMA International Conference on Cryptography and Coding, Oxford, United Kingdom, 12 December 2017.
S38 “Towards Low Energy Block Ciphers”, seminar at Working Groups Meeting, Cryptacus COST Action, Nijmegen, The Netherlands, 17 November 2017.
S37 “Physical Attacks and Beyond”, seminar at Mobile System Technologies Workshop, Milano, Italy, 27 October 2017.
S36 “Low Energy, a new trend for lightweight cryptography”, seminar at University of California Irvine, Irvine, California, USA, 1 February 2017.
S35 “MIDORI: A Block Cipher for Low Energy”, seminar at Boston University, Electrical & Computer Engineering, Boston, Massachusetts, USA, 15 July 2016.
S34 “MIDORI: A Block Cipher for Low Energy”, seminar at Virginia Tech, Blacksburg, Virginia, USA, 6 May 2016.
S33 “Security Challenges at Hardware Design Time for mobile systems”, seminar at University of Passau, Passau, Germany, 25 June 2015.
S32 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at George Mason University, Fairfax, Virginia, USA, 14 May 2015.
S31 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at University of California Irvine, Irvine, California, USA, 3 March 2015.
S30 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at Qualcomm, San Diego, California, USA, 5 December 2014.
S29 “Stealthy Dopant-Level Hardware Trojans”, seminar at Columbia University, New York, New York, USA, 3 December 2014.
S28 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at NEC Laboratories, Tokyo, Japan, 15 May 2014.
S27 “Can you trust your hardware?”, seminar at Technische Universität Berlin, Berlin, Germany, 31 March 2014.
S26 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at , University of Passau, Passau, Germany 16 January 2014.
S25 “Can you trust you hardware?”, seminar at Computer Systems Architecture group, University of Amsterdam, Amsterdam, The Netherlands, 11 December 2013.
S24 “Design and implementation of a 5Gbit/s quantum random number generator”, seminar at Université Catholique de Louvain, Louvain-la-Neuve, Belgium, 2 October 2013.
S23 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at Columbia University, New York, New York, USA, 30 August 2013.
S22 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at New York University Polytechnic, New York, New York, USA, 29 August 2013.
S21 “Towards the Automatic Application and Verification of Countermeasures Against Physical Attacks”, seminar at Department of Computer Science and Engineering - University of California San Diego, La Jolla, California, USA, 26 August 2013.
S20 “Towards the Automatic Application of Countermeasures Against Physical Attacks”, seminar at Virginia Tech, Blacksburg, Virginia, USA, 10 June 2013.
S19 “Towards the Automation of Power Analysis Countermeasures”, seminar at University of Bristol, Bristol, United Kingdom, 25 March 2013.
S18 “Towards the Automatic Application of Countermeasures Against Physical Attacks”, seminar at Cryptography Working Group, Utrecht, The Netherlands, 1 March 2013.
S17 “Towards the Automatic Application of Countermeasures Against Physical Attacks”, seminar at Radboud University, Nijmegen, The Netherlands, 15 February 2013.
S16 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Boston University, Electrical & Computer Engineering, Boston, Massachusetts, 20 April 2012.
S15 “Towards the Automatic Application of Countermeasures Against Physical Attacks”, seminar at Department of Electrical and Computer Engineering - University of Massachusetts, Amherst, Massachusetts, USA, 18 April 2012.
S14 “Towards the Automatic Application of Countermeasures Against Side Channel Attacks”, seminar at Computer Science Department, Saarland University, Saarbrucken, Germany, 30 March 2012.
S13 “Side Channel Attacks, Introduction and Application to Embedded Processors”, seminar at IDQuantique S.A., Carouge, Switzerland, 20 February 2012.
S12 “Implementation and Evaluation of Random Number Generators”, seminar at Delft University of Technology, Delft, The Netherlands, 20 June 2011.
S11 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Czech Technical University in Prague, Faculty of Information Technology, Prague, Czech Republic, 30 November 2011.
S10 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Laboratory of Algorithmics, Cryptology and Security, University of Luxembourg, Luxembourg, Luxembourg, 27 October 2011.
S9 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Coding and Cryptography Research Group, Nanyang Technological University, Singapore, Singapore, 26 September 2011.
S8 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Department of Electrical and Computer Engineering - University of Massachusetts, Amherst, Massachusetts, USA, 29 June 2011.
S7 “Towards Automatic Application of Power Analysis Countermeasures”, seminar at Department of Computer Science and Engineering - University of California San Diego, La Jolla, California, USA, 7 June 2011.
S6 “Design Tools to Protect Embedded Systems from Power Analysis Attacks”, seminar at Department of Computer Science and Engineering, University of California Riverside, Riverside, California, USA, October 22, 2010.
S5 “A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions”, seminar at COSIC - Katholieke Universiteit Leuven, Leuven-Heverlee, Belgium, January 22, 2010.
S4 “A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions”, seminar at IAIK - Technische Universität Graz, Graz, Austria, September 30, 2009.
S3 “DPA Resistant Design Flow and its Applications”, seminar at Inesc-ID, Lisboa, Portugal, July 25, 2008.
S2 “Hardware/Software Partitioning of Operating Systems: a Behavioral Synthesis Approach”, IEEE EDP 2006 Workshop, Monterey, California, USA, April 13-14 April, 2006.
S1 “Early power and performance optimization of algorithm implementation on ARM processors”, Exhibition theater of DATE 2006, Munich, Germany, March 6-10, 2006.