Christian Pilato Postdoctoral Researcher Faculty of Informatics - ALaRI institute University of Lugano
	E-mail: Phone:	firstname.lastname@usi.ch +39 (340) 903-2850	Mail:	Via G. Buffi, 13 6900 Lugano, Switzerland

Home

Publications

Research

Teaching

Software

Hardware security for heterogeneous architectures

• Dynamic taint propagation in hardware accelerators (in collaboration with NYU);
• Security-aware design of cyber-physical systems (in the context of the CERBERO H2020 project);

High-level synthesis of high-performance accelerators

• Development of BAMBU, an open-source framework for research in high-level synthesis;
• Accelerator memory microarchitecture to support the high-level synthesis of unmodified C code with complex data structures and memory operations;
• Comparison with state-of-the-art HLS tools (in collaboration with TU Delft and University of Toronto);
• Generation of dedicated memory subsystems based on polymorphic register files for the Maxeler platforms (in collaboration with Maxeler and Chalmers University);
• System-level methodology for the design and optimization of the accelerator local memories in high-throughput accelerators (Mnemosyne, open-source CAD tool);

Hardware/software co-design with limited hardware resources

• Co-design methodologies based on Ant Colony Optimization for hardware/software partitioning, optimizing tasks and communications with several constraints on the application and the architecture (e.g., limited resources) (in the context of the hArtes FP6 project);
• Extensions to BAMBU for multi-objective design space exploration based on genetic algorithms;
• Path-profiling techniques and estimation methods for supporting automatic parallelization;
• Virtual prototyping of heterogeneous architectures;

Self-adaptive and reconfigurable systems

• ACO-based methodologies to determine the characteristics of the reconfigurable regions (in the context of the FASTER FP7 project);
• High-level analysis and design of heterogenous systems taking into account the effects of partial dynamic reconfiguration;
• FPGA prototyping of SoC architectures with accelerators processing massive data sets and featuring dynamic voltage and frequency scaling;